Alliance Memory DDR3L SDRAM

Alliance Memory DDR3L SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.

Features

V_DD = V_DDQ = 1.35V (1.283-1.45V)
Backward compatible to V_DD = V_DDQ = 1.5V ±0.075V
Supports DDR3L devices to be backward compatible in 1.5V applications
Differential bidirectional data strobe
8n-bit prefetch architecture
Differential clock inputs (CK, CK#)
8 internal banks
Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
Programmable CAS (READ) latency (CL)
Programmable posted CAS additive latency (AL)
Programmable CAS (WRITE) latency (CWL)
Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS])
Selectable BC4 or BL8 on-the-fly (OTF)
Self-refresh mode
TC of 0°C to +95°C
64ms, 8192-cycle refresh at 0°C to +85°C
32ms at +85°C to +95°C

Self-refresh temperature (SRT)
Automatic self-refresh (ASR)
Write leveling
Multipurpose register
Output driver calibration
Configuration
- 2 Gig x 4
- 1 Gig x 8
- 512 Meg x 16
- FBGA package (Pb-free) - x4, x8
- 78-ball (9x13.2mm)
- FBGA package (Pb-free) - x16
- 96-ball (9x14mm)
- Timing - cycle time
- 938ps @ CL = 14 (DDR3-2133)
- 1.07ns @ CL = 13 (DDR3-1866)
- 1.25ns @ CL = 11 (DDR3-1600)
Operating temperature:
- Commercial (0°C ≤ TC ≤ +95°C)
- Industrial (-40°C ≤ TC ≤ +95°C)