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Computing technologies and computing power continues to advance while the size of the computing components shrinks. The advancements in computing over the last couple of decades have been nothing short of astounding. but Still, limits exist to which bulk materials can reduce computing component size. .
Nanotechnology has been suggested as the solution for a while because top-down nanofabrication methods can help create smaller nanopatterning architectures out of bulk materials. Bottom-up methods can create ultra-small nanomaterials that are much smaller than would be possible by other manufacturing approaches. While several nanomaterials are used for next-generation computing technologies, interest exists in 2D materials due to their ultra-thin size, the degree of potential customizability on their surface, and their electronic properties―which range from highly conducting to semiconducting in nature depending on the 2D materials.
When it comes to computing approaches, computation tasks can be divided into two general areas: perception and reasoning. Perception involves object recognition and language processing operations and is facilitated by parallel matrix computing. On the other hand, serial logic computing is employed for solving reasoning tasks.
The current state-of-the-art computer architectures revolve around the von Neumann architecture with physically separated computing and memory units. However, users try to apply this single architecture to both perception and reasoning tasks. But perception and reasoning tasks have different computational requirements, making it challenging for a single architecture to perform both to the best of its ability.
On one hand, the data shuttling rate between the processing unit and the memory unit is limited for perception tasks, and there could be a much higher performance potential when solving reasoning tasks. However, computing architectures need a higher degree of transistors per area to achieve higher performance for reasoning tasks. While much progress has been made to scale down the size of transistors and pack more into a defined area of a chip, silicon is limited in how small it can be fabricated into small-scale transistors.
When you go below 3nm thickness, the properties of silicon-based transistors start to degrade. Even if designers can make silicon transistors small, silicon transistors may not be the best option. Other materials could be a better and more efficient alternative. This is where 2D materials come in. Because their inherent thinness, 2D materials can be used to make ultra-small transistors—as well as other nano-level devices—while not suffering from performance degradation. 2D materials offer a potential solution for scaling down the size of the transistors in these architectures to create more efficient logic-based architectures, while at the same time, they present an opportunity to create more efficient memory-based devices for matrix-based computing operations.
A number of different 2D materials can be employed, from the highly conductive sheets of graphene to the various semiconducting transition metal dichalcogenides (TMDCs) to the highly insulating nature of hexagonal boron nitride (h-BN). Each of the 2D materials out there—of which there are hundreds thanks to the TMDC class—all have unique characteristics that can be exploited, and their properties can be easily tailored. In addition, 2D materials can be physically—not chemically—stacked on top of each other to create van der Waals (vdW) heterostructures, that not only use the characteristics of the layers within the material, but each specific combination infers unique properties to the heterostructure―making 2D materials a highly customizable and versatile class of materials when creating ultra-small structures and devices.
One of the defining features of 2D materials, which also gives rise to their name, is that their electrons are confined in one dimension and can move freely in two dimensions. This electron confinement allows the 2D material sheets to have more precise control of the gate voltage. In addition, it offers the potential to be immune to the short-channel effect, which is when the channel length is relative in order of magnitude to the depletion-layer widths of the source and drain junction.
The atomic-scale thickness of 2D materials could offer an alternative material solution to use quantum effects and build more efficient computer hardware―and offer an alternative to the status quo where existing material architectures can’t keep scaling down effectively.
As mentioned above, one of the key areas where 2D materials could help to facilitate more tailored computing options is in matrix computing applications. In matrix computing applications, memory and transistor-based devices are the core components depending on the architecture. Designers can use a number of 2D materials to create memory and transistor devices―including ionic transistors, memtransistors, flash memory, and vdW heterostructures FETs.
The characteristics and properties of 2D materials give rise to improved memory performance and the potential to build 2D memory device arrays for more efficient matrix computing operations. The use of 2D materials also offers a method of boosting matrix computing operations because they impart a lower power consumption, a higher degree of precision and tunability, and either the NAND or NOR and can overcome some of the common challenges that bulk memory devices exhibit in these areas.
There is interest in using 2D material-based matrix computing architecture in AI-centric applications, specifically neural networks. The memory cells in these applications need to meet specific requirements. In the case of artificial neural networks (ANNs), 2D materials could meet the requirements of the non-volatile memory devices that need a specific amplitude input signal encoding system.
On the other hand, for spiking neural networks (SNNs), the integration of 2D material memory devices and ionic transistors is offers a realistic implementation of biomimicry. 2D materials that are grown by chemical vapor deposition (CVD) can contain a number of defects, and while this may not be beneficial in some areas, it is useful for biomimicry applications as it leads to anisotropic transport properties that facilitate ion migration and coupling between devices―in a similar way that neural synapses work in the natural world.
Aside from the interest in neural networks, designers are also investigating 2D material-based magnetic memory devices for matrix computing applications. The properties of 2D materials improve the performance of these devices, but still barriers exist with these technologies because there’s a need to find 2D materials that provide higher environmental tolerances than what have been tested so far.
The other area of interest for 2D materials devices is logic computing applications. In logic computing, the physical challenge of: scaling down the devices and increasing transistor density needs solving. As you scale down to ultra-small levels, the scaling of the voltage becomes stagnant with many materials due to the current leakage from the thin-film dielectric materials used alongside the conductive sections. So, 2D materials are being tested for these applications because they retain their beneficial properties at scales that other materials cannot.
In current silicon-on-insulator technology, it is possible to create very thin channel transistors; however, the mobility of the charge carriers in silicon below 3nm thickness degrades very quickly, unlike in 2D materials where the charge carrier properties stay efficient. Because there are insulating 2D materials as well as conducting, designers can stack the layers on top of each other, as well as stacking conductive/semiconducting 2D layers on to conventional insulating substrates. This allows 2D material transistors to reap the same benefits as silicon-on-insulator technology without the performance degradation at lower scales, improve performance in the steep subthreshold swing and driving current, and achieve greater immunity to the short channel effect.
The ability to stack 2D materials into vdW heterostructures also opens more doors for logic computing applications, including more area-efficient logic gate structures and the ability to integrate the heterostructures without any lattice mismatching issues. When it comes to computing chips, a number of logic gates are used and either the NAND or NOR gate can be used to construct the whole logic system. In bulk architectures, only the top surface is used in the device design, requiring two input terminals (two transistors). However, when designers use 2D materials to build similar logic systems, only one transistor terminal is needed for the input signal because both the top and bottom surfaces of the channel materials can be tuned effectively.
Benefits could also exist when it comes to the vertical integration of chips―a common way to increase chip density. Bulk materials contain lattice distortions that cause them to suffer from a low interconnection density. However, when it comes to 2D materials, there’s no need to design for any lattice adaptation because the 2D materials are grown directly into the target substrate and redundant materials are etched away. Any subsequent layers, if heterostructures are being fabricated, are grown on top of the previous functional layer. There are also no limitations between the neighboring functional layers in vdW heterostructures, so each layer can be stacked independently, regardless of whether it’s a computing layer or a memory layer. Designers could employ this approach in the future to increase the data movement energy efficiency and data transfer rate in future logic-based computing architectures.
As we start scaling down computing architectures to build the next generation of computing hardware, it might be advisable to create systems specifically designed for logic or matrix-based applications. The small scale and electronic properties of 2D materials offer a way to develop:
So, while it may take some time to implement, there’s much potential for 2D materials in future computing applications.
Liam Critchley is a writer, journalist and communicator who specializes in chemistry and nanotechnology and how fundamental principles at the molecular level can be applied to many different application areas. Liam is perhaps best known for his informative approach and explaining complex scientific topics to both scientists and non-scientists. Liam has over 350 articles published across various scientific areas and industries that crossover with both chemistry and nanotechnology.
Liam is Senior Science Communications Officer at the Nanotechnology Industries Association (NIA) in Europe and has spent the past few years writing for companies, associations and media websites around the globe. Before becoming a writer, Liam completed master’s degrees in chemistry with nanotechnology and chemical engineering.
Aside from writing, Liam is also an advisory board member for the National Graphene Association (NGA) in the U.S., the global organization Nanotechnology World Network (NWN), and a Board of Trustees member for GlamSci–A UK-based science Charity. Liam is also a member of the British Society for Nanomedicine (BSNM) and the International Association of Advanced Materials (IAAM), as well as a peer-reviewer for multiple academic journals.