Bench Talk

(Source: ZinetroN - stock.adobe.com)

"Reduced Instruction Set Computer V", RISC-V for short, was developed at the University of California at Berkeley by Krste Asanovic and David A. Patterson together with industrial partners. The project grew out of a series of academic research programs on parallel software and hardware development.

The Berkeley Source Distribution (BSD) license is a key differentiator from other instruction set architectures (ISAs). It allows users to design, manufacture, and sell RISC-V cores without royalties, while proprietary implementations don't have to be open to customers or competitors.

Is RISC-V Permanent?

One of the goals of RISC-V was a small, open ISA optimized for fast, powerful, and energy-efficient processors. It can be easily implemented in FPGAs, ASICs and custom CPUs, and supports all microarchitectures, most programming languages, and software stacks. The ISA is fixed so that code written today will continue to run on future processor cores if they use the same base ISA with identical extensions.

RISC-V International, the successor to the RISC-V Foundation, oversees the technology. The original authors and owners have transferred their rights to this foundation.

RISC-V provides three different base ISAs: RVI32I for 32-bit hardware, RV64I for 64-bit, and RV128I for 128-bit. A special variant of the RVI32I for embedded systems is RV32E with only 16 registers.

The RV32I commands are based on six formats:

1. Command Type R: Register-to-Register Operations
2. Command Type I: Short Immediates and Load Operations
3. Command Type S: Saving Data Words
4. Command Type B: Conditional Branching
5. Command Type U: Upper Immediates
6. Command Type J: Jump Statements

These formats are the basis for integer commands such as control, load/save, register manipulation, and debugging. In RV32I, all these instructions are 32 bits wide and use only one clock cycle. This is very different from other ISAs, such as ARM-32 or x86-32, where the commands require several cycles.

In recent years, many manufacturers have developed RISC-V cores, CPUs, and MCUS, which has allowed the technology to mature and overcome initial problems.

Silicon with a Modern ISA

One of the pioneer companies for RISC-V cores is Andes Technology, a member of RISC-V International. Its current flagship product is the AX45MP 64-bit core.

This multicore CPU IP is an 8-stage superscalar processor based on the AndeStar V5 architecture. It supports the standard RISC-V extensions "G (IMAC-FD)", the 16-bit compression commands "C", the DSP/SIMD extension "P" (draft), the user-level interrupt extension "N" and the Andes performance/function extensions for faster memory access and branch processing, as well as the Andes Custom Extension (ACE) for adding custom commands. It features an MMU for Linux-based applications, branch prediction for efficient branch execution, Level 1 command/data caches, and local storage for low-latency access.

The AX45MP symmetric multiprocessor supports up to four cores and a Level 2 cache controller with command and data prefetching. The Coherence Manager implements the MESI protocol to manage Level 1 cache coherence, including I/O coherence for non-cached bus masters. Other features of the AX45MP include ECC for soft error protection in Level 1/2 storage, Platform-Level Interrupt Controller (PLIC) with extensions for vectored dispatch and priority-based preemption, CoDense, StackSafe to improve software quality, and QuickNap, PowerBrake, and WFI for power management.

Renesas Electronics has implemented this core in working silicon. The RZ/Five microprocessor includes a 1.0GHz RISC-V CPU core (AX45MP Single) and a 16-bit DDR3L/DDR4 interface. It also has numerous interfaces, such as Gbit Ethernet, CAN, and USB 2.0, making it suitable for applications such as entry-level social infrastructure gateway control and industrial gateways (Figure 1).

Figure 1: Block diagram of the RZ/Five Microprocessor (Source: Renesas)

The RZ/Five (Figure 2) is offered in 13mm x 13mm BGA-361 and 11mm x 11mm BGA-266 packages. The BGA-361 variant contains a 2-channel Gigabit Ethernet interface. The BGA-266 variant offers a 1-channel Gigabit Ethernet interface.

Figure 2: The RZ/Five RISC-V Microprocessor (Source: Mouser Electronics)

The evaluation board helps determine whether the RZ/Five is suitable for solving design problems. It provides a complete demonstration and development platform for the RZ/Five RISC-V microprocessor. The RZ/Five MPU features a 1.0GHz RISC-V CPU core (AX45MP Single) and a 16-bit DDR3L/DDR4 interface. The device also has a variety of interfaces such as Gbit Ethernet, CAN, and USB 2.0, making it ideal for controlling social infrastructure gateways and entry-level industrial gateways.

The evaluation board kit consists of a module board (SOM) (Figure 3) and a carrier board. The carrier board can also be used with RZ/G2L, RZ/G2LC, and RZ/V2L modules based on the SMARC v2.1 standard. This design allows the user a seamless and flexible evaluation between these devices.

Figure 3: Module Board Structure (Source: Renesas)

The Future for RISC-V

The open architecture combined with the modern pipeline system makes RISC-V cores a serious threat to closed, proprietary IP cores. The absence of delayed branches and status codes allows for a lean CPU structure. As more hardware design and manufacturing companies implement RISC-V silicon, this instruction set could play a very dominant role in the semiconductor market.

Marcel Consée is a Technical Content Specialist at Technical Marketing EMEA. The studied physicist and trained journalist has been active in the electronics industry for over 20 years.